LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY clock IS PORT (EN
:IN STD_LOGIC;数码管使能
CLK
:IN STD_LOGIC;时钟信号
RST
:IN STD_LOGIC;复位信号
SEC_1
:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);秒高位
SEC_01 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);秒低位
MIN_1
:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);分高位
MIN_01 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);分低位
HOU_1
:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);时高位
HOU_01 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);时低位
BEE
:OUT STD_LOGIC ); END clock;
ARCHITECTURE behovior OF clock IS SIGNAL SEC_HIGH:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL SEC_LOW
:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL MIN_HIGH:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL MIN_LOW:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL HOU_HIGH:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL HOU_LOW
:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CY_MIN
:STD_LOGIC;分进位
SIGNAL CY_HOU
:STD_LOGIC;时进位
SIGNAL LOGO_1
:STD_LOGIC;标志
SIGNAL LOGO_2
:STD_LOGIC;
SIGNAL LOGO_3
:STD_LOGIC;
BEGIN MIAOLOW:PROCESS(CLK,RST,EN)
BEGIN
IF(RST = \'0\')
THEN
SEC_LOW
ELSIF(CLK\'EVENT AND CLK = \'1\' AND EN = \'1\') THEN 检测时钟上升沿及数码管使能端
IF(SEC_LOW = \"1001\") THEN
SEC_LOW
ELSE
SEC_LOW
END IF;
END IF;
END PROCESS MIAOLOW;
LOGO_1
SEC_01
MIAOHIGH:PROCESS(CLK,RST)
BEGIN
IF(RST = \'0\')
THEN
SEC_HIGH
ELSIF(CLK\'EVENT AND CLK = \'1\') THEN检测时钟上升沿
IF(LOGO_1 = \'1\') THEN
IF(SEC_HIGH = \"0101\") THEN
SEC_HIGH
CY_MIN
ELSE
SEC_HIGH
CY_MIN
END IF;
END IF;
END IF;
END PROCESS MIAOHIGH;
SEC_1
FENLOW:PROCESS(CY_MIN,RST,EN)
BEGIN
IF(RST = \'0\')
THEN 若复位位为0
MIN_LOW
ELSIF(CY_MIN\'EVENT AND CY_MIN = \'1\' AND EN = \'1\') THEN检测时钟上升沿及数码管使能端
IF(MIN_LOW = \"1001\") THEN
MIN_LOW
ELSE
MIN_LOW
END IF;
END IF;
END PROCESS FENLOW;
LOGO_2
MIN_01
FENHIGH:PROCESS(CY_MIN,RST)
BEGIN
IF(RST = \'0\')
THEN
MIN_HIGH
ELSIF(CY_MIN\'EVENT AND CY_MIN = \'1\') THEN检测分进位上升沿
IF(LOGO_2 = \'1\') THEN
IF(MIN_HIGH = \"0101\") THEN若分十位为5
MIN_HIGH
CY_HOU
ELSE
MIN_HIGH
CY_HOU
END IF;
END IF;
END IF;
END PROCESS FENHIGH;
MIN_1
SHILOW:PROCESS(CY_HOU,RST,EN)
BEGIN
IF(RST = \'0\')
THEN
HOU_LOW
ELSIF(CY_HOU\'EVENT AND CY_HOU = \'1\'
AND EN = \'1\') THEN检测时进位上升沿及数码管使能端
IF(HOU_LOW = \"1001\") THEN若时低位为9
HOU_LOW
ELSIF(HOU_HIGH = \"0010\" AND HOU_LOW = \"0011\") THEN若时十位为2，个位为3
HOU_LOW
ELSE
HOU_LOW
END IF;
END IF;
END PROCESS SHILOW;
LOGO_3
HOU_01
SHIHIGH:PROCESS(CY_HOU,RST)
BEGIN
IF(RST = \'0\')
THEN
HOU_HIGH
ELSIF(CY_HOU\'EVENT AND CY_HOU = \'1\') THEN检测时进位上升沿
IF (HOU_HIGH = \"0010\" AND HOU_LOW = \"0011\") THEN若时十位为2，时个位为3
HOU_HIGH
ELSIF(LOGO_3 = \'1\') THEN
HOU_HIGH
END IF;
END IF;
END PROCESS SHIHIGH;
BEE_CLOCK:PROCESS(CLK)
BEGIN
IF(CLK\'EVENT AND CLK = \'1\') THEN检测时钟上升沿
IF(SEC_HIGH = \"0101\" AND SEC_LOW = \"1001\"
AND MIN_HIGH = \"0101\" AND MIN_LOW = \"1001\") THEN
BEE
ELSE
BEE
END IF;
END IF;
END PROCESS BEE_CLOCK;
HOU_1
END behovior;
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY clock1 IS PORT (EN
:IN STD_LOGIC;
CLK
:IN STD_LOGIC;
RST
:IN STD_LOGIC; SEC_1
:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SEC_01 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0); MIN_1
:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
MIN_01 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0); HOU_1
:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
HOU_01 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
BEE
:OUT STD_LOGIC ); END clock1;
ARCHITECTURE behovior OF clock1 IS SIGNAL SEC_HIGH:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL SEC_LOW
:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL MIN_HIGH:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL MIN_LOW:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL HOU_HIGH:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL HOU_LOW
:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CY_MIN
:STD_LOGIC;
SIGNAL CY_HOU
:STD_LOGIC; SIGNAL LOGO_1
:STD_LOGIC;
SIGNAL LOGO_2
:STD_LOGIC;
SIGNAL LOGO_3
:STD_LOGIC;
BEGIN MIAOLOW:PROCESS(CLK,RST,EN)
BEGIN
IF(RST = \'0\')
THEN
SEC_LOW
ELSIF(CLK\'EVENT AND CLK = \'1\' AND EN = \'1\') THEN
IF(SEC_LOW = \"1001\") THEN
SEC_LOW
ELSE
SEC_LOW
END IF;
END IF;
END PROCESS MIAOLOW;
LOGO_1
SEC_01
MIAOHIGH:PROCESS(CLK,RST)
BEGIN
IF(RST = \'0\')
THEN
SEC_HIGH
ELSIF(CLK\'EVENT AND CLK = \'1\') THEN
IF(LOGO_1 = \'1\') THEN
IF(SEC_HIGH = \"0101\") THEN
SEC_HIGH
CY_MIN
ELSE
SEC_HIGH
CY_MIN
END IF;
END IF;
END IF;
END PROCESS MIAOHIGH;
SEC_1
BEGIN
IF(RST = \'0\')
THEN
MIN_LOW
ELSIF(CY_MIN\'EVENT AND CY_MIN = \'1\' AND EN = \'1\') THEN
IF(MIN_LOW = \"1001\") THEN
MIN_LOW
ELSE
MIN_LOW
END IF;
END IF;
END PROCESS FENLOW;
LOGO_2
MIN_01
FENHIGH:PROCESS(CY_MIN,RST)
BEGIN
IF(RST = \'0\')
THEN
MIN_HIGH
ELSIF(Cy_MIN\'EVENT AND CY_MIN = \'1\') THEN
IF(LOGO_2 = \'1\') THEN
IF(MIN_HIGH = \"0101\") THEN
MIN_HIGH
CY_HOU
ELSE
MIN_HIGH
CY_HOU
END IF;
END IF;
END IF;
END PROCESS FENHIGH;
MIN_1
BEGIN
IF(RST = \'0\')
THEN
HOU_LOW
ELSIF(CY_HOU\'EVENT AND CY_HOU = \'1\' AND EN = \'1\') THEN
IF(HOU_LOW = \"1001\") THEN
HOU_LOW
ELSIF(HOU_HIGH = \"0010\" AND HOU_LOW = \"0011\") THEN
HOU_LOW
ELSE
HOU_LOW
END IF;
END IF;
END PROCESS SHILOW;
LOGO_3
HOU_01
SHIHIGH:PROCESS(Cy_HOU,RST)
BEGIN
IF(RST = \'0\')
THEN
HOU_HIGH
ELSIF(CY_HOU\'EVENT AND CY_HOU = \'1\') THEN
IF (HOU_HIGH = \"0010\" AND HOU_LOW = \"0011\") THEN
HOU_HIGH
ELSIF(LOGO_3 = \'1\') THEN
HOU_HIGH
END IF;
END IF;
END PROCESS SHIHIGH;
BEE_CLOCK:PROCESS(CLK)
BEGIN
IF(CLK\'EVENT AND CLK = \'1\') THEN
IF(SEC_HIGH = \"0101\" AND SEC_LOW = \"1001\"
AND MIN_HIGH = \"0101\" AND MIN_LOW = \"1001\") THEN
BEE
ELSE
BEE
END IF;
END IF;
END PROCESS BEE_CLOCK;
HOU_1
END behovior;
