12-Bit A/D Converter
CIRCUIT OPERATION The AD574A is a complete 12-bit A/D converter which requires no external components to provide the complete succeive approximation analog-to-digital conversion function.A block diagram of the AD574A is shown in Figure 1.
Figure 1.Block Diagram of AD574A 12-Bit A-to-D Converter
When the control section is commanded to initiate a conversion (as described later), it enables the clock and resets the succeiveapproximation register (SAR) to all zeros.Once a conversion cycle has begun, it cannot be stopped or restarted and data is not available from the output buffers.The SAR, timed by the clock, will sequence through the conversion cycle and return an end-of-convert flag to the control section.The control section will then disable the clock, bring the output status flag low, and enable control functions to allow data read functions by external command.
During the conversion cycle, the internal 12-bit current output DAC is sequenced by the SAR from the most significant bit (MSB) to least significant bit (LSB) to provide an output current which accurately balances the input signal current through the 5kΩ(or10kΩ) input resistor.The comparator determines whether the addition of each succeively-weighted bit current causes the DAC current sum to be greater or le than the input current; if the sum is le, the bit is left on; if more, the bit is turned off.After testing all the bits, the SAR contains a 12-bit binary code which accurately represents the input signal to within 1/2 LSB.
The temperature-compensated buried Zener reference provides the primary voltage reference to the DAC and guarantees excellent stability with both time and temperature.The reference is trimmed to 10.00 volts 0.2%; it can supply up to 1.5 mA to an external load in addition to the requirements of the reference input resistor (0.5 mA) and bipolar offset resistor (1 mA) when the AD574A is powered from 15 V supplies.If the AD574A is used with 12 V supplies, or if external current must be supplied over the full temperature range, an external buffer amplifier is recommended.Any external load on the AD574A reference must remain constant during conversion.The thin-film application resistors are trimmed to match the full-scale output current of the DAC.There are two 5 kinput scaling resistors to allow either a 10 volt or 20 volt span.The 10 kbipolar offset resistor is grounded for unipolar operation and connected to the 10 volt reference for bipolar operation.DRIVING THE AD574 ANALOG INPUT
Figure 2.Op Amp – AD574A Interface
The output impedance of an op amp has an open-loop value which, in a closed loop, is divided by the loop gain available at the frequency of interest.The amplifier should have acceptable loop gain at 500 kHz for use with the AD574A.To check whether the output properties of a signal source are suitable, monitor the AD574’s input with an oscilloscope while a conversion is in progre.Each of the 12 disturbances should subside in sorle.
For applications involving the use of a sample-and-hold amplifier, the AD585 is recommended.The AD711 or AD544 op amps are recommended for dc applications. SAMPLE-AND-HOLD AMPLIFIERS Although the conversion time of the AD574A is a maximum of 35 s, to achieve accurate 12-bit conversions of frequencies greater than a few Hz requires the use of a sample-and-hold amplifier (SHA).If the voltage of the analog input signal driving the AD574A changes by more than 1/2 LSB over the time interval needed to make a conversion, then the input requires a SHA.
The AD585 is a high linearity SHA capable of directly driving the analog input of the AD574A.The AD585’s fast acquisition time, low aperture and low aperture jitter are ideally suited for high-speed data acquisition systems.Consider the AD574A converter with a 35 s conversion time and an input signal of 10 V p-p: the maximum frequency which may be applied to achieve rated accuracy is 1.5 Hz.However, with the addition of an AD585, as shown in Figure 3, the maximum frequency increases to 26 kHz.The AD585’s low output impedance, fast-loop response, and low droop maintain 12-bits of accuracy under the changing load conditions that occur during a conversion, making it suitable for use in high accuracy conversion systems.Many other SHAs cannot achieve 12-bits of accuracy and can thus compromise a system.The AD585 is recommended for AD574A applications requiring a sample and hold.
Figure 3.AD574A with AD585 Sample and Hold
SUPPLY DECOUPLING AND LAYOUT CONSIDERATIONS It is critically important that the AD574A power supplies be filtered, well regulated, and free from high frequency noise.Use of noisy supplies will cause unstable output codes.Switching power supplies are not recommended for circuits attempting to achieve 12-bit accuracy unle great care is used in filtering any switching spikes present in the output.Remember that a few millivolts of noise represents several counts of error in a 12-bit ADC.Circuit layout should attempt to locate the AD574A, aociated analog input circuitry, and interconnections as far as poible from logic circuitry.For this reason, the use of wire-wrap circuit construction is not recommended.Careful printed circuit construction is preferred.UNIPOLAR RANGE CONNECTIONS FOR THE AD574A The AD574A contains all the active components required to perform a complete 12-bit A/D conversion.Thus, for most situations, all that is neceary is connection of the power supplies (+5 V, +12 V/+15 V and –12 V/–15 V), the analog input, and the conversion initiation command, as discued on the next page.Analog input connections and calibration are easily accomplished; the unipolar operating mode is shown in Figure 4.
Figure 4.Unipolar Input Connections
All of the thin-film application resistors of the AD574A are trimmed for absolute calibration.Therefore, in many applications, no calibration trimming will be required.The absolute accuracy for each grade is given in the specification tables.For example, if no trims are used, the AD574AK guarantees 1 LSB max zero offset error and 0.25% (10 LSB) max full-scale error.(Typical full-scale error is 2 LSB.) If the offset trim is not required, Pin 12 can be connected directly to Pin 9; the two resistors and trimmer for Pin 12 are then not needed.If the full-scale trim is not needed, a 50 1% metal film resistor should be connected between Pin 8 and Pin 10. The analog input is connected between Pin 13 and Pin 9 for a 0 V to +10 V input range, between 14 and Pin 9 for a 0 V to +20 V input range.The AD574A easily accommodates an input signal beyond the supplies.For the 10 volt span input, the LSB has a nominal value of 2.44 mV; for the 20 volt span, 4.88 mV.If a 10.24 V range is desired (nominal 2.5 mV/bit), the gain trimmer (R2) should be replaced by a 50Ωesistor, and a 200Ωtrimmer inserted in series with the analog input to Pin 13 for a full-scale range of 20.48 V (5 mV/bit), use a 500 trimmer into Pin 14.The gain trim described below is now done with these trimmers.The nominal input impedance into Pin 13 is 5kΩ, and 10kΩinto Pin 14.UNIPOLAR CALIBRATION The AD574A is intended to have a nominal 1/2 LSB offset so that the exact analog input for a given code will be in the middle of that code (halfway between the transitions to the codes above and below it).Thus, the first transition (from 0000 0000 0000 to 0000 0000 0001) will occur for an input level of +1/2 LSB (1.22 mV for 10 V range).If Pin 12 is connected to Pin 9, the unit will behave in this manner, within specifications.If the offset trim (R1) is used, it should be trimmed as above, although a different offset can be set for a particular system requirement.This circuit will give approximately 15 mV of offset trim range.The full-scale trim is done by applying a signal 1/2 LSB below the nominal full scale (9.9963 for a 10 V range).Trim R2 to give the last transition (1111 1111 1110 to 1111 1111 1111).BIPOLAR OPERATION The connections for bipolar ranges are shown in Figure 5.Again, as for the unipolar ranges, if the offset and gain specifications are sufficient, one or both of the trimmers shown can be replaced by a 50 1% fixed resistor.Bipolar calibration is similar to unipolar calibration.
Figure 5.Bipolar Input Connections
CONTROL LOGIC The AD574A contains on-chip logic to provide conversion initiation and data read operations from signals commonly available in microproceor systems.Figure 6 shows the internal logic circuitry of the AD574A.The control signals CE, CS, and R/C control the operation of the converter.The state of R/C when CE and CS are both aerted determines whether a data read (R/C = 1) or a convert (R/C = 0) is in progre.The register control inputs AO and 12/8 control conversion length and data format.The AO line is usually tied to the least significant bit of the addre bus.If a conversion is started with AO low, a full 12-bit conversion cycleis initiated.If AO is high during a convert start, a shorter 8-bit conversion cycle results.During data read operations, AO determines whether the three-state buffers containing the 8 MSBs of the conversion result (AO = 0) or the 4 LSBs (AO = 1) are enabled.The 12/8 pin determines whether the output data is to be organized as two 8-bit words (12/8 tied to DIGITAL COMMON) or a single 12-bit word (12/8 tied to VLOGIC).The 12/8 pin is not TTL-compatible and must be hard-wired to either VLOGIC or DIGITAL COMMON.In the 8-bit mode, the byte addreed when AO is high contains the 4 LSBs from the conversion followed by four trailing zeroes.This organization allows the data lines to be overlapped for direct interface to 8-bit buses without the need for external three-state buffers.It is not recommended that AO change state during a data read operation.Asymmetrical enable and disable times of the three-state buffers could cause internal bus contention resulting in potential damage to the AD574A.
Figure 6.AD574A Control Logic An output signal, STS, indicates the status of the converter.STS goes high at the beginning of a conversion and returns low when the conversion cycle is complete.TIMING The AD574A is easily interfaced to a wide variety of microproceors and other digital systems.The following discuion of the timing requirements of the AD574A control signals should provide the system designer with useful insight into the operation of the device.Figure 7 shows a complete timing diagram for the AD574A convert start operation.R/C should be low before both CE and CS are aerted; if R/C is high, a read operation will momentarily occur, poibly resulting in system bus contention.Either CE or CS may be used to initiate a conversion; however, use of CE is recommended since it includes one le propagation delay than CS and is the faster input.In Figure 7, CE is used to initiate the conversion.
Figure 7
Once a conversion is started and the STS line goes high, convert start commands will be ignored until the conversion cycle is complete.The output data buffers cannot be enabled during conversion.Figure 8 shows the timing for data read operations.During data read operations, acce time is measured from the point where CE and R/C both are high (auming CS is already low).If CS is used to enable the device, acce time is extended by 100 ns.
Figure 8.Read Cycle Timing
In the 8-bit bus interface mode (12/8 input wired to DIGITAL COMMON), the addre bit, AO, must be stable at least 150 ns prior to CE going high and must remain stable during the entire read cycle.If AO is allowed to change, damage to the AD574A output buffers may result.“STAND-ALONE” OPERATION The AD574A can be used in a ―stand-alone‖ mode, which is useful in systems with dedicated input ports available and thus not requiring full bus interface capability.In this mode, CE and 12/8 are wired high, CS and AO are wired low, and conversion is controlled by R/C.The three-state buffers are enabled when R/C is high and a conversion starts when R/C goes low.This allows two poible control signals—a high pulse or a low pulse.Operation with a low pulse is shown in Figure 11.In this case, the outputs are forced into the high impedance state in response to the falling edge of R/C and return to valid logic levels after the conversion cycle is completed.The STS line goes high 600 ns after R/C goes low and returns low 300 ns after data is valid.
Figure 11.Low Pulse for R/C—Outputs Enabled After Conversion
If conversion is initiated by a high pulse as shown in Figure 12, the data lines are enabled during the time when R/C is high.The falling edge of R/C starts the next conversion, and the data lines return to three-state (and remain three-state) until the next high pulse of R/C.
Figure 12.High Pulse for R/C—Outputs Enabled While R/C High, Otherwise High-Z
Usually the low pulse for R/C stand-alone mode will be used.Figure 13 illustrates a typical stand-alone configuration for 8086 type proceors.The addition of the 74F/S374 latches improves bus acce/release times and helps minimize digital feedthrough to the analog portion of the converter.INTERFACING THE AD574A TO MICROPROCESSORS The control logic of the AD574A makes direct connection to most microproceor system buses poible.While it is impoible to describe the details of the interface connections for every microproceor type, several representative examples will be described here.GENERAL A/D CONVERTER INTERFACE CONSIDERATIONS A typical A/D converter interface routine involves several operations.First, a write to the ADC addre initiates a conversion.The proceor must then wait for the conversion cycle to complete, since most ADCs take longer than one instruction cycle to complete a conversion.Valid data can, of course, only be read after the conversion is complete.The AD574A provides an output signal (STS) which indicates when a conversion is in progre.This signal can be polled by the proceor by reading it through an external three-state buffer (or other input port).The STS signal can also be used to generate an interrupt upon completion of conversion, if the system timing requirements are critical (bear in mind that the maximum conversion time of the AD574A is only 35 microseconds) and the proceor has other tasks to perform during the ADC conversion cycle.Another poible time-out method is to aume that the ADC will take 35 microseconds to convert, and insert a sufficient number of ―do-nothing‖ instructions to ensure that 35 microseconds of proceor time is consumed
Once it is established that the conversion is finished, the data can be read.In the case of an ADC of 8-bit resolution (or le), a single data read operation is sufficient.In the case of converters with more data bits than are available on the bus, a choice of data formats is required, and multiple read operations are needed.The AD574A includes internal logic to permit direct interface to 8-bit or 16-bit data buses, selected by connection of the 12/8 input.In 16-bit bus applications (12/8 high) the data lines (DB11 through DB0) may be connected to either the 12 most significant or 12 least significant bits of the data bus.The remaining four bits should be masked in software.The interface to an 8-bit data bus (12/8 low) is done in a left-justified format.The even addre (A0 low) contains the 8 MSBs (DB11 through DB4).The odd addre (A0 high) contains the 4 LSBs (DB3 through DB0) in the upper half of the byte, followed by four trailing zeroes, thus eliminating bit masking instructions.SPECIFIC PROCESSOR INTERFACE EXAMPLES Z-80 System Interface The AD574A may be interfaced to the Z-80 proceor in an I/O or memory mapped configuration.Figure 15 illustrates an I/O or mapped configuration.The Z-80 uses addre lines A0–A7 to decode the I/O port addre.An interesting feature of the Z-80 is that during I/O operations a single wait state is automatically inserted, allowing the AD574A to be used with Z-80 proceors having clock speeds up to 4 MHz.For applications faster than 4 MHz use the wait state generator in Figure 16.In a memory mapped configuration the AD574A may be interfaced to Z-80 proceors with clock speeds of up to 2.5 MHz.
